This invention relates to clock signal fan out within integrated circuit (IC) chips and, specifically, to a method of deskewing clock signals at various levels of a multilevel clock tree.
Conventional integrated circuits (ICs) use a clock signal and branch it out through a series of buffers to form a plurality of clock signals. The structure of the branching of the clock signal is called a xe2x80x9cclock tree.xe2x80x9d One or more clock trees can be present in a single IC. For example, a clock signal at a given branch, or level, of the clock tree may feed into three buffers to produce three clock signals at the next level, which may each feed into three more buffers to produce nine clock signals at the third level. The clock signals at any level of the clock tree are sent to various synchronous components of the IC to coordinate the functions of these components. For various reasons, however, any two clock signals, even at the same level of the same clock tree, may be slightly different or offset from each other. This difference in clock signals is called xe2x80x9cclock skew,xe2x80x9d and differences throughout several clock signals of any level of the clock tree is called xe2x80x9cclock tree skewxe2x80x9d.
Clock tree skew has several causes. For example, the buffers between levels in the clock tree typically introduce a delay between their input and output clock signals, so clock signals at different levels of the clock tree are usually naturally skewed from each other. Additionally, the load experienced by one clock signal may introduce a delay into the clock signal different from that of another load on another clock signal. Furthermore, changes in temperature, different applied voltages and differing semiconductor fabrication processes can affect the clock skew. Such other causes of clock skew are typically due to temperature variations, circuit load variations, different applied voltages, different semiconductor fabrication processes and inadequate tolerances in the semiconductor fabrication process.
One prior art device employs a power PC chip which has buffers with multiple trees to drive a large bus. Performance is less than optimal because changes in the rise and fall times of these many drivers slows system operation.
Another prior art device relied on a neighboring clock signal for deskewing in which each finally derived clock signal drove the active components of the integrated circuit. This device consumed a notable area of semiconductor substrate and was somewhat susceptible to process, voltage, and temperature variations.
There is a need to provide a method to reliably generate multiple levels of well calibrated clock signals which requires minimal semiconductor substrate area and has reduced susceptibility to process, voltage, and temperature variations.
The present invention enables dynamic self-detection and correction of clock tree skew in an integrated circuit (IC) using a multilevel clock tree. Each level has a temporary clock buffer or reference signal which is used to deskew the variable delay clock buffer signals. Several temporary clock buffer signals are generated at each level. By designing their signal paths to be the same length and geometry, the temporary clock buffer signals of a given level are synchronized. Only the variable delay clock buffer signals proceed to the next level of the multilevel clock tree.
Clock skew variations due to temperature changes, different applied voltages and different semiconductor fabrication processes are corrected at each level of the multilevel clock tree. Thus, as clock skew increases or decreases during operation of the IC, the present invention may dynamically detect and correct the changing clock skew on-the-fly. In this manner, the adjustment of each clock signal in a clock tree does not rely on a single determination and adjustment of the anticipated clock skew during the design of the IC, but is altered and re-altered as is dynamically determined to be appropriate by a skew detection and adjustment circuitry, particularly in response to differences in applied voltage, temperature and fabrication process. The design combines signal path length balancing with temporary clock buffers for calibration. The clock skew of every variable delay clock buffer signal of each level may be independently set as circumstances warrant.
In the skew detection and adjustment circuitry of the present invention, each variable delay clock buffer signal in a clock tree is paired with a temporary clock buffer signal at each level in the clock tree. The absolute skew between the two clock signals in each pair is detected, and the variable delay clock buffer signal of each pair is adjusted forward or backward as appropriate. Such adjustment of the clock signals is performed by adding or subtracting a certain amount of delay. The detection and adjustment is repeated in increments as necessary to reach an acceptable minimum skew. Thus, the invention has the advantage of automatically correcting for almost any amount of clock skew. Additionally, since the skew detection and adjustment circuitry may dynamically detect and correct absolute skew between a pair consisting of a temporary clock buffer signal and a variable clock delay buffer signal, the invention has the further advantage of automatically correcting for clock skew variations due to different applied voltages and/or different semiconductor fabrication processes that could not be anticipated during the design of the IC. The detection and adjustment may be performed during the operation of the IC to account for changing clock skew patterns or it may be performed as needed.
The clock tree deskew circuit preferably includes a plurality of skew adjust circuits and a corresponding plurality of skew detect circuits. The clock tree deskew circuit of a level also preferably sends output clock signals to either the synchronized circuit components or to the next level of the clock tree. Each skew adjust circuit corresponds to and produces one of the variable delay clock buffer signals. The skew detect circuits connect to their corresponding skew adjust circuits to receive the corresponding variable delay clock buffer signal. Each skew detect circuit also receives a temporary clock buffer signal. Each skew detect circuit produces an adjustment signal to its corresponding skew adjust circuit indicative of whether the variable delay clock signal preceded the temporary buffer signal. Each skew adjust circuit preferably receives the adjustment signal and shifts the corresponding variable delay clock buffer signal accordingly.
The multilevel clock tree of the present invention may be arranged such that each level is concentric to the others. This arrangement helps provide symmetry for the temporary clock buffer signal paths to ensure synchronization of the temporary clock buffer signals through the matching of signal path geometry and path length. The present invention provides an improvement over current methods in being able to adjust clock skew over temperature, process, and voltage variations and on the fly within just a few clock cycles.
In a portable device which incorporates an integrated circuit which has a multilevel clock tree of the present invention, a user may be able to selectively synchronize the timing of an integrated circuit having the multilevel clock tree. This would allow the user to synchronize the timing when he suddenly goes out doors or experiences a change of environment or climate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.